Programmable logic devices (PLDs) are a well-known type of integrated circuit (“IC”) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) field-effect transistor (“FET”) (e.g., a P-type MOS (“PMOS”) FET) paired with a second-conductivity-type MOS transistor (e.g., an N-type MOS (“NMOS”) FET). CMOS cells can hold a logic state while drawing only very small amounts of current.
The integrity of the gate dielectric (“gate oxide”) is important for holding a logic state. Defects in the gate oxide can provide current leakage paths that corrupt the logic state stored by the MOS FET. Such defects are often called “soft defects”. In some cases, defects in the gate oxide or other structures can cause a short circuit or open circuit between terminals of the device that destroys operability of the FET. Such defects are often called “killer defects”.
Some defects in the FET are observable. Electron-beam (“E-beam”) inspection techniques are typically used to inspect process wafers during a fabrication sequence for gate oxide and other defects. Such inspection is commonly referred to as “in-line” because the inspection step is incorporated into the fabrication process flow. In other words, process wafers can be inspected between fabrication steps without removing the wafer from the fabrication area, such as between front-end-of-line (“FEOL”) processes and back-end-of-line (“BEOL”) processes.
Some defects appear only after electrical stress is applied to the device. Defects arising from such stress tests are typically done off-line. That is, the wafer is removed from the fabrication sequence for stress testing. Techniques have been developed testing IC wafers that incorporate structures specifically designed to accelerate killer defects. Such structures are known for both accelerating and capturing defects occurring in the FEOL and in the BEOL. Generally, the scanning beam of an E-beam inspection system enhances contrast between good portions and defective portions of a test structure. An example of a technique for defect detection in the FEOL is described in Loop Before You Yield, by Akihiro Shimada et al., KLA-Tencor Yield Management Solutions, Winter 2005, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. Techniques for identifying defects of a semiconductor test structure in the BEOL processes are described in U.S. Pat. No. 6,445,199 B1, issued Sep. 3, 2002 to Satya et al., the disclosure of which is hereby incorporated by reference in its entirely for all purposes.
However, these techniques only detect processing (intrinsic) defects. In order to detect stress-related (also called extrinsic or reliability) defects, such as oxide reliability, electrical stress needs to be applied to the device. Techniques for in-line detection of extrinsic (stress) defects are desirable to provide improved processing feedback and improved device reliability.